ST72F521 datasheet(202/215 Pages) STMICROELECTRONICS

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ST72F521, ST72521B

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ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

OPT2 = Reserved, must be kept at default value.

OPT1= PKG0 Package selection bit 0

This option bit is used to select the package (see

table in PKG1 option bit description).

OPT0= FMP_R Flash memory read-out protection

Read-out protection, when selected, provides a

protection against Program Memory content ex-

traction and against write access to Flash memo-

ry.

Erasing the option bytes when the FMP_R option

is selected causes the whole user memory to be

erased first, and the device can be reprogrammed.

Refer to Section 4.3.1 and the ST7 Flash Pro-

gramming Reference Manual for more details.

Note: Readout protection is not supported if LVD

is enabled.

0: Read-out protection enabled

1: Read-out protection disabled

OPTION BYTE 1

OPT7= PKG1 Package selection bit 1

This option bit, with the PKG0 bit, selects the pack-

age.

Note: On the chip, each I/O port has 8 pads. Pads

that are not bonded to external pins are in input

pull-up configuration after reset. The configuration

of these pads must be kept at reset state to avoid

added current consumption.

OPT6 = RSTC RESET clock cycle selection

This option bit selects the number of CPU cycles

applied during the RESET phase and when exiting

HALT mode. For resonator oscillators, it is advised

to select 4096 due to the long crystal stabilization

time.

0: Reset phase with 4096 CPU cycles

1: Reset phase with 256 CPU cycles

OPT5:4 = OSCTYPE[1:0] Oscillator Type

These option bits select the ST7 main clock

source type.

OPT3:1 = OSCRANGE[2:0] Oscillator range

When the resonator oscillator type is selected,

these option bits select the resonator oscillator

current source corresponding to the frequency

range of the used resonator. Otherwise, these bits

are used to select the normal operating frequency

range.

OPT0 = PLLOFF PLL activation

This option bit activates the PLL which allows mul-

tiplication by two of the main input clock frequency.

The PLL must not be used with the internal RC os-

cillator or with external clock source. The PLL is

guaranteed only with an input frequency between

2 and 4MHz.

0: PLL x2 enabled

1: PLL x2 disabled

CAUTION: the PLL can be enabled only if the

“OSC RANGE” (OPT3:1) bits are configured to

“MP - 2~4MHz”. Otherwise, the device functionali-

ty is not guaranteed.

Version

Selected Package

PKG 1 PKG 0

MTQFP80

(A)R

TQFP64

Clock Source

OSCTYPE

Resonator Oscillator

Reserved

Internal RC Oscillator

External Source

Typ. Freq. Range

OSCRANGE

210

1~2MHz

2~4MHz

4~8MHz

8~16MHz

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