ST72F521 datasheet(211/215 Pages) STMICROELECTRONICS

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ST72F521, ST72521B

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15 KNOWN LIMITATIONS

15.1 ALL FLASH AND ROM DEVICES

15.1.1 External RC option

The External RC clock source option described in

previous datasheet revisions is no longer support-

ed and has been removed from this specification.

15.1.2 Safe Connection of OSC1/OSC2 Pins

The OSC1 and/or OSC2 pins must not be left un-

connected otherwise the ST7 main oscillator may

start and, in this configuration, could generate an

fOSC clock frequency in excess of the allowed

maximum (>16MHz.), putting the ST7 in an un-

safe/undefined state. Refer to section 6.2 on page

25.

15.1.3 Reset pin protection with LVD Enabled

As mentioned in note 2 below Figure 103 on page

186, when the LVD is enabled, it is recommended

not to connect a pull-up resistor or capacitor. A

10nF pull-down capacitor is required to filter noise

on the reset line.

15.1.4 Unexpected Reset Fetch

If an interrupt request occurs while a “POP CC” in-

struction is executed, the interrupt controller does

not recognise the source of the interrupt and, by

default, passes the RESET vector address to the

CPU.

Workaround

To solve this issue, a “POP CC” instruction must

always be preceded by a “SIM” instruction.

15.1.5

Clearing

active

interrupts

outside

interrupt routine

When an active interrupt request occurs at the

same time as the related flag is being cleared, an

unwanted reset may occur.

Note: clearing the related interrupt mask will not

generate an unwanted reset

Concurrent interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

Perform SIM and RIM operation before and after

resetting an active interrupt request.

Example:

SIM

reset interrupt flag

RIM

Nested interrupt context:

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine with higher or identical priority level

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

PUSH CC

SIM

reset interrupt flag

POP CC

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