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LAN9252/ML Scheda tecnica(PDF) 184 Page - Microchip Technology |
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LAN9252/ML Scheda tecnica(HTML) 184 Page - Microchip Technology |
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184 / 329 page ![]() LAN9252 DS00001909A-page 184 2015 Microchip Technology Inc. 11.2.16.29 PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x) Note 21: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg- ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. Index (In Decimal): 3.32865 Size: 16 bits Bits Description Type Default 15:0 Physical Address [47:32] R/W/ NASR Note 21 FFFFh |
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