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STM32H523VCU6 Scheda tecnica(PDF) 141 Page - STMicroelectronics |
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STM32H523VCU6 Scheda tecnica(HTML) 141 Page - STMicroelectronics |
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141 / 228 page ![]() DS14540 Rev 1 141/228 STM32H523xx Electrical characteristics 197 5.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 56). Unless otherwise specified, the parameters in Table 66 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 19. 11 Fmax(2)(4) Maximum frequency C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 30 MHz C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 35 C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 44 C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 55 C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 77 tr/tf(3)(4) Output high to low level fall time and output low to high level rise time C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 11.1 ns C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 9.2 C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 7.2 C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5.4 C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 3.6 1. Specified by design - Not tested in production. 2. The maximum frequency is defined with the conditions: (tr+tf) ≤ 2/3 T, Skew ≤ 1/20 T, 45%<Duty cycle<55%. 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 4. Compensation system enabled. Table 64. Output timing characteristics VDDIO2 1.2 V (HSLV ON)(1) (continued) Speed Symbol Parameter Conditions Min Max Unit Table 65. Output timing characteristics for FT_c I/Os (PB13/PB14)(1)(2) Speed Symbol Parameter Conditions Min Max Unit 00 Fmax Maximum frequency C = 50 pF, 2.7 V ≤ VDDIO ≤ 3.6 V - 2 MHz C = 50 pF, 1.71 V ≤ VDDIO < 2.7 V - 1 tr/tf Output rise and fall time C = 50 pF, 2.7 V ≤ VDDIO < 3.6 V - 166 ns C = 50 pF, 1.71 V ≤ VDDIO < 2.7 V - 330 01 Frmax Maximum frequency C = 30 pF, 2.7 V ≤ VDDIO < 3.6 V - 10 MHz C = 30 pF, 1.71 V ≤ VDDIO < 2.7 V - 4 tr/tf Output rise and fall time C = 30 pF, 2.7 V ≤ VDDIO < 3.6 V - 33 ns C = 30 pF, 1.71 V ≤ VDDIO < 2.7 V - 65 1. Specified by design - Not tested in production. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO port configuration register. |
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