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STM32H523VCU6 Scheda tecnica(PDF) 171 Page - STMicroelectronics |
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STM32H523VCU6 Scheda tecnica(HTML) 171 Page - STMicroelectronics |
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171 / 228 page ![]() DS14540 Rev 1 171/228 STM32H523xx Electrical characteristics 197 Figure 41. ADC conversion timing diagram 6 bits 47 2.14E-08 3.16E-08 68 2.23E-08 3.21E-08 100 2.40E-08 3.31E-08 150 2.68E-08 3.52E-08 220 3.13E-08 3.87E-08 330 3.89E-08 4.51E-08 470 4.88E-08 5.39E-08 680 6.38E-08 6.79E-08 1000 8.70E-08 8.97E-08 1500 1.23E-07 1.24E-07 2200 1.73E-07 1.73E-07 3300 2.53E-07 2.49E-07 4700 3.53E-07 3.45E-07 6800 5.04E-07 4.90E-07 10000 7.34E-07 7.11E-07 15000 1.09E-06 1.05E-06 1. Specified by design - Not tested in production. 2. Data valid up to 130 °C, with a 22 pF PCB capacitor, and VDDA = 1.6 V. 3. Slow channels correspond to all ADC inputs except for the fast channels. Table 90. Minimum sampling time versus RAIN(1)(2) (continued) Resolution RAIN (Ω) Minimum sampling time (s) Fast channel Slow channel(3) CLK 1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details). Sampling (1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mux Number of CLK clock cycles = ADC resolution / 2 Total conversion time: 0.5 +Tsamp + N/2 SMP 1/2 |
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