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STM32F207VCY7V Scheda tecnica(PDF) 137 Page - STMicroelectronics

Il numero della parte STM32F207VCY7V
Spiegazioni elettronici  ARM®-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/1284KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  184 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F207VCY7V Scheda tecnica(HTML) 137 Page - STMicroelectronics

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STM32F20xxx
Electrical characteristics
183
Synchronous waveforms and timings
Figure 61 through Figure 64 represent synchronous waveforms, and Table 77 through
Table 79 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
•
MemoryType = FSMC_MemoryType_CRAM;
•
WriteBurst = FSMC_WriteBurst_Enable;
•
CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual)
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period.
th(A_NWE)
Address hold time after FSMC_NWE high
THCLK– 0.5
-
ns
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
THCLK- 1
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0.5
ns
tv(Data_NADV)
FSMC_NADV high to Data valid
-
THCLK+2
ns
th(Data_NWE)
Data hold time after FSMC_NWE high
THCLK– 0.5
-
ns
1. CL = 30 pF.
2. Guaranteed by characterization results, not tested in production.
Table 75. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) (continued)
Symbol
Parameter
Min
Max
Unit



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