Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

Preview PDF HTML

STM32F429NET7 Scheda tecnica(PDF) 187 Page - STMicroelectronics

Il numero della parte STM32F429NET7
Spiegazioni elettronici  ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT
PDF  231 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F429NET7 Scheda tecnica(HTML) 187 Page - STMicroelectronics

Back Button STM32F429NET7 Datasheet HTML 183Page - STMicroelectronics STM32F429NET7 Datasheet HTML 184Page - STMicroelectronics STM32F429NET7 Datasheet HTML 185Page - STMicroelectronics STM32F429NET7 Datasheet HTML 186Page - STMicroelectronics STM32F429NET7 Datasheet HTML 187Page - STMicroelectronics STM32F429NET7 Datasheet HTML 188Page - STMicroelectronics STM32F429NET7 Datasheet HTML 189Page - STMicroelectronics STM32F429NET7 Datasheet HTML 190Page - STMicroelectronics STM32F429NET7 Datasheet HTML 191Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 187 / 231 page
background image
DocID024030 Rev 6
187/231
STM32F427xx STM32F429xx
Electrical characteristics
192
Table 104. SDRAM write timings(1)(2)
1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK.
2. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
ns
td(SDCLKL _Data)
Data output valid time
-
3.5
th(SDCLKL _Data)
Data output hold time
0
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL_SDNWE)
SDNWE valid time
-
1
th(SDCLKL_SDNWE)
SDNWE hold time
0
-
td(SDCLKL_ SDNE)
Chip select valid time
-
0.5
th(SDCLKL-_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
2
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
0.5
td(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
td(SDCLKL_NBL)
NBL valid time
-
0.5
th(SDCLKL_NBL)
NBLoutput time
0
-
Table 105. LPSDR SDRAM write timings(1)(2)
1. CL = 10 pF.
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
ns
td(SDCLKL _Data)
Data output valid time
-
5
th(SDCLKL _Data)
Data output hold time
2
-
td(SDCLKL_Add)
Address valid time
-
2.8
td(SDCLKL-SDNWE)
SDNWE valid time
-
2
th(SDCLKL-SDNWE)
SDNWE hold time
1
-
td(SDCLKL- SDNE)
Chip select valid time
-
1.5
th(SDCLKL- SDNE)
Chip select hold time
1
-
td(SDCLKL-SDNRAS)
SDNRAS valid time
-
1.5
th(SDCLKL-SDNRAS)
SDNRAS hold time
1.5
-
td(SDCLKL-SDNCAS)
SDNCAS valid time
-
1.5
td(SDCLKL-SDNCAS)
SDNCAS hold time
1.5
-
td(SDCLKL_NBL)
NBL valid time
-
1.5
th(SDCLKL-NBL)
NBL output time
1.5
-



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com