L9963E datasheet(139/184 Pages) STMICROELECTRONICS

139 / 184 page

6.6.2

Cell balancing with external MOSFETs

Figure 38. Cell monitoring with external balancing with the mixed NMOS and PMOS transistors

C10

S10

B10_9

RLPF

RDRV

CLPF

L9963E

•

Force lines used for

balancing. Connect them as

close as possible to the cell

connector. This improves

cell voltage sensing while

balancing is ongoing, by

minimizing the voltage drop

on the sense lines while

current is being sunk

•

Sense lines used for cell

voltage measurement. Keep

away from noisy lines.

Recommended PCB layout

strategy is to route them

over the first layer and

shield them using the

second layer as GND plane

RDIS

Table 78. External balancing components with recommended values

Components Value

Unit

Max.

tolerance

Rating

Comments

RDRV

kΩ

10%

1/10 W

The drop on RDRV generates the VGS = VCELL to turn on

the external balance FET. Max 3.3 kΩ. Values lower than

the recommended one can be used when both internal and

external paths have to be exploited for balancing. However,

current in the internal balancing path must not exceed 200

mA. Maximum internal cell balance current in application is

IBALmax=VCELLmax

RDRV

RDIS

Ω

10%

3 W

Any value is possible, as long as the cell balance current

does not exceed the maximum drain current of the external

FET. Maximum external cell balance current in application is

IBALmax=VCELLmax

RDIS

The BSS308PE is recommended for the balancing of even

cells

The 2V7002K is recommended for the balancing of odd cells

6.7

FAULT line circuit

The FAULT Line implementation varies according to the system topology. In all cases, fault signal follows a

monodirectional approach, propagating in the top-down direction. Transceivers are not included in the fault line

and can be bypassed.

L9963E

FAULT line circuit

DS13636 - Rev 12

page 139/184

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