IS25LE02GG-RHLA2:P-TY datasheet(104/187 Pages) ISSI

Il numero della parte	IS25LE02GG-RHLA2:P-TY

Spiegazioni elettronici	SERIAL FLASH MEMORY 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	187 Pages

Scroll/Zoom	100%

Produttore elettronici	ISSI [Integrated Silicon Solution, Inc]

Homepage	http://www.issi.com

Logo

104 / 187 page

IS25LE02GG

IS25WE02GG

Integrated Silicon Solution, Inc.- www.issi.com

104

Rev. A1

10/02/2025

8.25 ENTER DEEP POWER DOWN (DP, B9h)

The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter

into Power-down mode). During this mode, standby current is reduced from Isb1 to Isb2. While in the Power-down

mode, the device is not active and all Write/Program/Erase instructions are ignored. The instruction is initiated by

driving the CE# pin low and shifting the instruction code into the device. The CE# pin must be driven high after the

instruction has been latched, or Power-down mode will not engage. Once CE# pin driven high, the Power-down

mode will be entered within the time duration of tDP. While in the Power-down mode only ABh instruction, which

restores the device to normal operation, will be recognized. All other instructions are ignored, including the Read

Status Register instruction which is always available during normal operation. Ignoring all but one instruction makes

the Power Down state a useful condition for securing maximum write protection. It is available in both SPI and QPI

mode.

Figure 8.56 Enter Deep Power Down Mode Sequence In SPI Mode

Instruction = B9h

CE #

SCK

Mode 3

Mode 0

tDP

High Impedance

Figure 8.57 Enter Deep Power Down Mode Sequence In QPI Mode

B9h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

tDP

IS25LE02GG-RHLA2:P-TY Scheda tecnica(PDF) 104 Page - Integrated Silicon Solution, Inc