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GD32H757VMT7 Scheda tecnica(PDF) 127 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757VMT7 Scheda tecnica(HTML) 127 Page - GigaDevice Semiconductor (Beijing) Inc. |
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127 / 151 page ![]() GD32H757xx Datasheet 126 Figure 4-10. OSPI timing diagram - SDR mode Clock Data output Data input D0 D1 D2 D0 D1 D2 tSCK(H) tSCK(L) tCK tr(CK) tf(CK) tV(MO) tH(MO) tSU(MI) tH(MI) Figure 4-11. OSPI timing diagram - DTR mode Clock Data output Data input D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5 tSCK(H) tSCK(L) tCK tr(CK) tf(CK) tVF(SO) tVR(SO) tHR(SO) tHF(SO) tSUF(SI) tSUR(SI) tTHF(SI) tTHR(SI) 4.25. CPDM characteristics Table 4-59. CPDM characteristics Symbol Parameter Conditions Min(2) Typ(1) Max(2) Unit tinit Initial delay — 2 TBD 9 ps tΔ Unit Delay — 31 TBD 65 ps (1) Value guaranteed by characterization, not 100% tested in production. (2) Value guaranteed by design, not 100% tested in production. 4.26. HPDF characteristics Table 4-60. HPDF characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit fHPDFCLK HPDF clock — — fAPB2 fSYSCLK MHz fCKIN (1 / TCKIN) Input clock frequency SPI mode(SITYP[1:0] = 01) — — 20 (fHPDFCLK / 4) fCKOUT Output clock — — — 20 |
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