ST7FOXF1 datasheet(112/226 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7FOXF1, ST7FOXK1, ST7FOXK2

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Timebase Counter 2

Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR

stored in the LTARR register. A counter overflow event occurs when the counter rolls over

from FFh to the LTARR reload value. Software can write a new value at any time in the

LTARR register, this value will be automatically loaded in the counter when the next overflow

occurs.

When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an

interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software

reading the LTCSR2 register.

Figure 53.

Input Capture timing diagram

Watchdog

When enabled using the WDGE bit, the Watchdog generates a reset after 2 ms (@ = 8 MHz

fOSC).

To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is

cleared by hardware after tWDG. This means that software must write to the WDGD bit at

regular intervals to prevent a watchdog reset occurring. Refer to Figure 54.

Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.

A Watchdog reset can be forced at any time by setting the WDGRF bit.

The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the

reset. It is automatically cleared after it has been read.

Hardware Watchdog Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the

WDGE bit in the LTCSR1 is not used.

Refer to the Option byte description.

Using Halt mode with the Watchdog (option)

If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be

used when the watchdog is enabled.

04h

8-bit COUNTER 1

01h

fOSC/32

xxh

02h

03h

05h

06h

07h

04h

LTIC PIN

ICF FLAG

LTICR REGISTER

CLEARED

4µs

(@ 8 MHz fOSC)

fCPU

BY S/W

07h

READING

LTIC REGISTER

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