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T89C51CC02CA-RATIM Scheda tecnica(PDF) 126 Page - ATMEL Corporation |
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T89C51CC02CA-RATIM Scheda tecnica(HTML) 126 Page - ATMEL Corporation |
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126 / 145 page  126 T89C51CC02 4126D–CAN–05/03 Table 105. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 Reset Value = XXXX X000b bit addressable 765 43210 ---- POVRL PADCL PCANL Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2POVRL Timer Overrun Interrupt Priority Level Less Significant bit Refer to PI2CH for priority level. 1PADCL ADC Interrupt Priority Level Less Significant bit Refer to PSPIH for priority level. 0PCANL CAN Interrupt Priority Level Less Significant bit Refer to PKBH for priority level. |
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