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HD6432351 Scheda tecnica(PDF) 347 Page - Renesas Technology Corp

Il numero della parte HD6432351
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 Scheda tecnica(HTML) 347 Page - Renesas Technology Corp

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Section 8 Data Transfer Controller (DTC)
Rev. 3.00 Sep 15, 2006 page 313 of 988
REJ09B0330-0300
8.3.8
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 8.9 shows the memory map for chain transfer.
Source
Source
Destination
Destination
DTC vector
address
Register information
start address
Register information
CHNE = 1
Register information
CHNE = 0
Figure 8.9 Chain Transfer Memory Map
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.



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