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HD6432351 Scheda tecnica(PDF) 532 Page - Renesas Technology Corp |
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HD6432351 Scheda tecnica(HTML) 532 Page - Renesas Technology Corp |
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532 / 1025 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Sep 15, 2006 page 498 of 988 REJ09B0330-0300 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10.52 shows the timing in this case. Compare match signal Write signal Address φ Buffer register address Buffer register TGR write cycle T1 T2 N TGR N M Buffer register write data Figure 10.52 Contention between Buffer Register Write and Compare Match |
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