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HD6432351 Scheda tecnica(PDF) 552 Page - Renesas Technology Corp |
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HD6432351 Scheda tecnica(HTML) 552 Page - Renesas Technology Corp |
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552 / 1025 page ![]() Section 11 Programmable Pulse Generator (PPG) Rev. 3.00 Sep 15, 2006 page 518 of 988 REJ09B0330-0300 11.2.7 Port 1 Data Direction Register (P1DDR) 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W 0 P10DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W Bit Initial value R/W : : : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1. For further information about P1DDR, see section 9.2, Port 1. 11.2.8 Port 2 Data Direction Register (P2DDR) 7 P27DDR 0 W 6 P26DDR 0 W 5 P25DDR 0 W 4 P24DDR 0 W 3 P23DDR 0 W 0 P20DDR 0 W 2 P22DDR 0 W 1 P21DDR 0 W Bit Initial value R/W : : : P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. Port 2 is multiplexed with pins PO7 to PO0. Bits corresponding to pins used for PPG output must be set to 1. For further information about P2DDR, see section 9.3, Port 2. |
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