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HD6432351 Scheda tecnica(PDF) 156 Page - Renesas Technology Corp |
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HD6432351 Scheda tecnica(HTML) 156 Page - Renesas Technology Corp |
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156 / 1025 page ![]() Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 122 of 988 REJ09B0330-0300 • Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle • Write buffer functions External write cycle and internal access can be executed in parallel DMAC single-address mode and internal access can be executed in parallel • Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC • Other features Refresh counter (refresh timer) can be used as an interval timer External bus release function |
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