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HD6432351 Scheda tecnica(PDF) 186 Page - Renesas Technology Corp |
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HD6432351 Scheda tecnica(HTML) 186 Page - Renesas Technology Corp |
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186 / 1025 page ![]() Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 152 of 988 REJ09B0330-0300 8-Bit 3-State Access Space Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High Note: n = 0 to 7 T3 Figure 6.7 Bus Timing for 8-Bit 3-State Access Space |
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