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HD6432351 Scheda tecnica(PDF) 236 Page - Renesas Technology Corp |
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HD6432351 Scheda tecnica(HTML) 236 Page - Renesas Technology Corp |
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236 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 202 of 988 REJ09B0330-0300 7.2.1 Memory Address Registers (MAR) 16 * R/W 18 * R/W 17 * R/W Bit MAR Initial value R/W : : : : 19 * R/W 21 * R/W 22 * R/W 23 * R/W 24 — 0 — 25 — 0 — 26 — 0 — 27 — 0 — 28 — 0 — 29 — 0 — 30 — 0 — 31 — 0 — 0 * R/W 2 * R/W 1 * R/W 3 * R/W 4 * R/W 5 * R/W 6 * R/W 7 * R/W 8 * R/W 9 * R/W 10 * R/W 11 * R/W 12 * R/W 13 * R/W 14 * R/W 15 * R/W 20 * R/W *: Undefined Bit MAR Initial value R/W : : : : MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. |
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