HD64F2149YV datasheet(562/1075 Pages) RENESAS

Il numero della parte	HD64F2149YV

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 534 of 1044

REJ09B0280-0300

SDA

(slave output)

SDA

(master output)

SCL

(slave output)

Bit 7

Bit 6

Bit 5

Bit 7

Bit 6

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IRIC

ICDRS

ICDRT

TDRE

SCL

(master output)

Interrupt

request

generation

Interrupt

request

generation

Slave receive mode

Slave transmit mode

Data 1

Data 2

[3] IRIC

clearance

[5] IRIC

clearance

[3] ICDR write

[5] ICDR write

User processing

Data 1

Data 2

[3]

[2]

Interrupt

request

generation

Figure 16.11 Example of Slave Transmit Mode Operation Timing (MLS = 0)

16.3.6

IRIC Setting Timing and SCL Control

The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the

FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is

automatically held low after one frame has been transferred; this timing is synchronized with the

internal clock. Figure 16.11 shows the IRIC set timing and SCL control.

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