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HD64F2149YV Scheda tecnica(PDF) 777 Page - Renesas Technology Corp

Il numero della parte HD64F2149YV
Spiegazioni elettronici  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV Scheda tecnica(HTML) 777 Page - Renesas Technology Corp

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Section 24 Power-Down State
Rev. 3.00 Jan 18, 2006 page 749 of 1044
REJ09B0280-0300
Hardware
standby mode
STBY pin = low
Notes: • When a transition is made between modes by means of an interrupt, transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting
the interrupt request.
• From any state except hardware standby mode, a transition to the reset state occurs whenever
RES goes low.
• From any state, a transition to hardware standby mode occurs when
STBY goes low.
• When a transition is made to watch mode or subactive mode, high-speed mode must be set.
Sleep mode
(main clock)
SSBY = 0, LSON = 0
Software
standby mode
SSBY = 1
PSS = 0, LSON = 0
Watch mode
(subclock)
SSBY = 1
PSS = 1, DTON = 0
Subsleep mode
(subclock)
SSBY = 0
PSS = 1, LSON = 1
Medium-speed
mode
(main clock)
Subactive mode
(subclock)
High-speed
mode
(main clock)
Reset state
STBY pin = high
RES pin = low
RES pin = high
Program execution state
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
Clock switching
exception handling
after oscillation
setting time
(STS2 to STS0)
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 1
Clock switching
exception handling
SCK2 to
SCK0
≠ 0
SCK2 to
SCK0
= 0
Program-halted state
SLEEP
instruction
Any interrupt*3
SLEEP
instruction
External
interrupt*4
SLEEP
instruction
Interrupt*1,
LSON bit = 0
SLEEP
instruction
Interrupt*1,
LSON bit = 1
Interrupt*2
SLEEP instruction
: Transition after exception handling
: Power-down mode
1. NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts
2. NMI, IRQ0 to IRQ7, and WDT0 interrupts, WDT1 interrupt, TMR0 interrupt, TMR1 interrupt
3. All interrupts
4. NMI, IRQ0 to IRQ2, IRQ6, IRQ7
Figure 24.1 Mode Transitions



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