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HD64F2149YV Scheda tecnica(PDF) 153 Page - Renesas Technology Corp |
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HD64F2149YV Scheda tecnica(HTML) 153 Page - Renesas Technology Corp |
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153 / 1075 page ![]() Section 5 Interrupt Controller Rev. 3.00 Jan 18, 2006 page 125 of 1044 REJ09B0280-0300 ICR UI I Default priority determination Vector number Interrupt acceptance control and 3-level mask control Interrupt source Interrupt control modes 0 and 1 Figure 5.7 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode Interrupt Mask Bits Interrupt Control Mode I UI Selected Interrupts 00 * All interrupts (control level 1 has priority) 1 * NMI and address break interrupt 10 * All interrupts (control level 1 has priority) 1 0 NMI, address break and control level 1 interrupts 1 NMI and address break interrupt Legend: *: Don’t care |
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