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H8S/2212 Scheda tecnica(PDF) 724 Page - Renesas Technology Corp |
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H8S/2212 Scheda tecnica(HTML) 724 Page - Renesas Technology Corp |
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724 / 750 page ![]() Section 22 Electrical Characteristics Rev.6.00 Jun. 03, 2008 Page 676 of 698 REJ09B0074-0600 Condition A Condition B Condition C,D Item Symbol Min. Max. Min. Max. Min. Max. Unit Test Conditions SCI Input clock Asynchro- nous tScyc 4 — 4 — 4 — tcyc Figure 22.15 cycle Synchro- nous 6 — 6 — 6 — Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc Input clock rise time tSCKr — 1.5 — 1.5 — 1.5 tcyc Input clock fall time tSCKf — 1.5 — 1.5 — 1.5 Transmit data delay time tTXD — 150 — 60 — 40 ns Figure 22.16 Receive data setup time (synchronous) tRXS 150 — 60 — 40 — Receive data hold time (synchronous) tRXH 150 — 60 — 40 — A/D converter Trigger input setup time tTRGS 60 — 40 — 30 — ns Figure 22.17 TCK cycle time tTcyc 166.6 — 62.5 — 41.6 — ns Boundary scan TCK high level pulse width tTCKH 0.4 0.6 0.4 0.6 0.4 0.6 tTcyc TCK low level pulse width tTCKL 0.4 0.6 0.4 0.6 0.4 0.6 tTcyc Figure 22.18 TRST pulse width tTRSW 20 — 20 — 20 — tTcyc TRST setup time tTRSS 350 — 250 — 250 — ns Figure 22.19 TDI setup time tTDIS 80 — 30 — 20 — ns TDI hold time tTDIH 10 — 10 — 10 — TMS setup time tTMSS 80 — 30 — 20 — Figure 22.20 TMS hold time tTMSH 10 — 10 — 10 — TDO delay time tTDOD — 100 — 40 — 35 |
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