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H8SX/1663R Scheda tecnica(PDF) 317 Page - Renesas Technology Corp

Il numero della parte H8SX/1663R
Spiegazioni elettronici  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Scheda tecnica(HTML) 317 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 285 of 1468
REJ09B0412-0200
To ensure the row address hold time or read access time, one to three of Trw cycles in which the
row address output is retained can be inserted between the Tr and Tc1 cycles. The
RAS signal is
driven low in the Tr cycle and the column address is output in the Tc1 cycle. Set the bit according
to the DRAM to be used and the frequency of this LSI so that the row address hold time to the
rising edge of the RAS signal is ensured.
Figure 9.41 shows an access timing example when one Trw cycle is specified.
T
p
T
r
T
rw
T
c1
T
c2
Address bus
Row address
Column address
B
φ
RAS
LUCAS
LLCAS
WE
OE (RD)
WE
OE (RD)
Data bus
High
High
Read
Write
Data bus
BS
RD/
WR
Figure 9.41 Access Timing Example when One Trw Cycle is Specified (RAST=0, CAST=0)



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