SH7014 datasheet(132/754 Pages) RENESAS

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7. Cache Memory (CAC)

Rev.5.00 Sep. 27, 2007 Page 98 of 716

REJ09B0398-0500

7.4

Usage Notes

7.4.1

Cache Initialization

Always initialize the cache before enabling it. Specifically, use an address array write to write 0 to

all valid bits for all entries (256 times), that is,those in the address range H'FFFFF000 to

H'FFFFF3FFF.

7.4.2

Forced Access to Address Array and Data Array

While the cache is enabled, it is not possible to write to the address array or data array via the

CPU, or DMAC, and a read will return an undefined value. The cache must be disabled before

making a forced access to the address array or data array.

7.4.3

Cache Miss Penalty and Cache Fill Timing

When a cache miss occurs, a single idle cycle is generated as a penalty immediately before the

cache fill (access from external memory in the event of a cache miss), as shown in figure 7.5.

However, in the case of consecutive cache misses, idle cycles are not generated for the second and

subsequent cache misses, as shown in figure 7.6.

As the timing for a cache fill from normal space, the CS assert period immediately before the end

of the bus cycle (or the last bus cycle when two or four bus cycles are generated, such as in a word

access to 8-bit space) is extended by an additional cycle, as shown in figures 7.5 and 7.6.

Similarly, as the timing for a cache fill from DRAM space, the RAS assert period immediately

before the end of the bus cycle is extended by an additional cycle as shown in figure 7.7. In RAS

down mode, the next bus cycle is delayed by one cycle as shown in figure 7.8.

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