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SH7014 Scheda tecnica(PDF) 148 Page - Renesas Technology Corp

Il numero della parte SH7014
Spiegazioni elettronici  32-Bit RISC Microcomputer
PDF  754 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Scheda tecnica(HTML) 148 Page - Renesas Technology Corp

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8. Bus State Controller (BSC)
Rev.5.00 Sep. 27, 2007 Page 114 of 716
REJ09B0398-0500
8.2.4
Wait Control Register 2 (WCR2)
WCR2 is a 16-bit read/write register that specifies the number of access cycles for DRAM space
and CS space for DMA single address mode transfers.
Do not perform any DMA single address transfers before WCR2 is set.
WCR2 is initialized by power-on resets to H'000F, but is not initialized by software standbys.
Bit:
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
⎯
⎯
DDW1
DDW0
DSW3
DSW2
DSW1
DSW0
Initial value:
0
0
0
0
1
1
1
1
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 6
⎯Reserved: These bits always read as 0. The write value should always be 0.
Bits 5 and 4
⎯DRAM Space DMA Single Address Mode Access Wait Specification (DDW1,
DDW0): Specifies the number of waits for DRAM space access during DMA single address mode
accesses. These bits are independent of the DWW and DWR bits of the DCR.
Bit 5
DDW1
Bit 4
DDW0
Description
0
0
2-cycle (no wait) external wait disabled
(initial value)
1
3-cycle (1 wait) external wait disabled
1
0
4-cycle (2 wait) external wait enabled
1
5-cycle (3 wait) external wait enabled



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