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SH7014 Scheda tecnica(PDF) 167 Page - Renesas Technology Corp

Il numero della parte SH7014
Spiegazioni elettronici  32-Bit RISC Microcomputer
PDF  754 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Scheda tecnica(HTML) 167 Page - Renesas Technology Corp

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8. Bus State Controller (BSC)
Rev.5.00 Sep. 27, 2007 Page 133 of 716
REJ09B0398-0500
8.4.4
Burst Operation
High-Speed Page Mode: When the burst enable bit (BE) of the DCR is set, burst accesses can be
performed using high speed page mode. The timing is shown in figure 8.12. Wait cycles can be
inserted during burst accesses by using the DCR.
Tp
Tc1
Tc2
Tc1
Tc2
Tr
CK
Write
Read
Address
Data
RAS
CASx
RDWR
Data
RDWR
CASx
RAS
Row
Column
Column
Figure 8.12 DRAM Bus Cycle (High-Speed Page Mode)
RAS Down Mode: There are some instances where even if burst operation is selected, continuous
accesses to DRAM will not occur, but another space will be accessed instead part way through the
access. In such cases, if the
RAS signal is maintained at low level during the time the other space
is accessed, it is possible to continue burst operation at the time the next DRAM same row address
is accessed. This is called RAS down mode.
To use RAS down mode, set both the BE and RASD bits of the DCR to 1.
Figures 8.13 and 8.14 show operation in RAS up and down modes.



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