SH7721 datasheet(112/1524 Pages) RENESAS

112 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 50 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description



R/W

T Bit

Indicates true or false for compare instructions or carry

or borrow occurrence for an operation instruction with

carry or borrow. This bit can be specified by the SETT

and CLRT instructions in user mode.

At reset, this bit is undefined. This bit is not affected in

an exception handling state.

Note:

The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits

can be read or written in privileged mode.

(2)

Save Status Register (SSR)

The save status register (SSR) can be accessed only in privileged mode. Before entering the

exception, the contents of the SR register is stored in the SSR register. At reset, the SSR initial

value is undefined.

(3)

Save Program Counter (SPC)

The save program counter (SPC) can be accessed only in privileged mode. Before entering the

exception, the contents of the PC is stored in the SPC. At reset, the SPC initial value is undefined.

(4)

Global Base Register (GBR)

The global base register (GBR) is referenced as a base register in GBR indirect addressing mode.

At reset, the GBR initial value is undefined.

(5)

Vector Base Register (VBR)

The vector base register (VBR) can be accessed only in privileged mode. If a transition from reset

state to exception handling state occurs, this register is referenced as a base address. For details,

refer to section 7, Exception Handling. At reset, the VBR is initialized as H'00000000.

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