SH7721 datasheet(118/1524 Pages) RENESAS

Il numero della parte	SH7721

Spiegazioni elettronici	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 56 of 1458

REJ09B0033-0300

2.5.2

CPU Instruction Addressing Modes

The following table shows addressing modes and effective address calculation methods for

instructions executed by the CPU core.

Table 2.3

Addressing Modes and Effective Addresses for CPU Instructions

Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation Formula

direct

Effective address is register Rn.

(Operand is register Rn contents.)



indirect

@Rn

Effective address is register Rn contents.

indirect with

post-increment

@Rn+

Effective address is register Rn contents. A

constant is added to Rn after instruction

execution: 1 for a byte operand, 2 for a word

operand, 4 for a longword operand.

1/2/4

Rn + 1/2/4

After instruction execution

Byte: Rn + 1

→ Rn

Word: Rn + 2

→ Rn

Longword: Rn + 4

→ Rn

indirect with

pre-decrement

@–Rn

Effective address is register Rn contents,

decremented by a constant beforehand: 1 for a

byte operand, 2 for a word operand, 4 for a

longword operand.

Rn - 1/2/4

1/2/4

Rn - 1/2/4

Byte: Rn – 1

→ Rn

Word: Rn – 2

→ Rn

Longword: Rn – 4

→ Rn

(Instruction executed with

Rn after calculation)

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