SH7721 datasheet(156/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 94 of 1458

REJ09B0033-0300

The RS and RE registers must be specified appropriately according to the rules shown in table 3.4.

The SH assembler supports control macros (REPEAT) as shown in table 3.6 to solve problems.

Table 3.6

Repeat Control Macros

Instruction

Operation

Number of

Execution States

REPEAT RptStart,

RptEnd, #imm

Specifies RptStart as repeat start instruction, RptEnd as

repeat end instruction, and 8-bit immediate data #imm

as number of repetitions. This macro is extended to

three instructions: LDRS, LDRE, and SETRC which are

converted correctly.

REPEAT RptStart,

RptEnd, Rm

Specifies RptStart as repeat start instruction, RptEnd as

repeat end instruction, and the [11:0] bits of Rm as

number of repetitions. This macro is extended to three

instructions: LDRS, LDRE, and SETRC which are

converted correctly.

Using the repeat macros shown in table 3.4, examples 1 to 4 shown above can be simplified to

examples 5 to 8 as shown below.

• Example 5: Repeat loop consisting of 4 or more instructions (extended to the instruction

stream shown in example 1, above)

REPEAT RptStart, RptEnd, #4

Instr0

;

RptStart: instr1

; [Repeat start instruction]

... ...

;

... ...

;

instr(N-3)

;

instr(N-2)

;

instr(N-1)

;

Rptend:

instrN

; [Repeat end instruction]

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