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7721 Group User’s Manual

13-2

DMA CONTROLLER

13.1 Overview

The DMA controller (hereafter called DMAC) transfers data using the bus and bypassing the CPU. DMAC

of the M37721 provides four independent channels of DMA0–DMA3, which have the same function each.

In this chapter, the source and destination of each DMA transfer are represented as follows.

q Memory

A device which needs its own address to be specified

Examples: Internal RAM and SFRs, external memory, and memory-mapped I/Os

q I/O

A device which does not need its own address to be specified

Example: External I/O devices

13.1.1 Performance overview

Table 13.1.1 lists the performance overview.

Table 13.1.1 DMAC performance overview

Item

Performance specifications

Number of channels

Transfer space

Number of transfer

bytes

DMA request source

Channel priority

Transfer rate

Data transfer

method

Transfer unit

Address direction of

transfer

Transfer mode

Continuous transfer

mode

4 channels

16 Mbytes (between arbitrary spaces)

Maximum of 16 Mbytes

Internal 14 sources and External 1 source

Fixed or Rotating

Maximum of 12.5 Mbytes/sec (at f(XIN) = 25 MHz, 1-bus cycle transfer)

Maximum of 6.25 Mbytes/sec (at f(XIN) = 25 MHz, 2-bus cycle transfer)

1-bus cycle or 2-bus cycle transfer

8 or 16 bits

Fixed, Forward, or Backward

(Directions of source and destination are independently selectable.)

Burst transfer or Cycle-steal transfer mode

Single transfer, Repeat transfer, Array chain transfer, or Link array chain transfer

mode

13.1 Overview

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