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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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M38044F2HKP Scheda tecnica(PDF) 175 Page - Renesas Technology Corp |
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M38044F2HKP Scheda tecnica(HTML) 175 Page - Renesas Technology Corp |
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175 / 387 page  2-51 APPLICATION 2.4 Serial interface Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) Fig. 2.4.6 Structure of UART1 control register Fig. 2.4.7 Structure of UART3 control register UART1 control register b7 b6 b5 b4 b3 b2 b1 b0 UART1 control register (UART1CON: address 001B16) b 0 0 0: 8 bits 1: 7 bits Character length selection bit (CHAS) Parity enable bit (PARE) Stop bit length selection bit (STPS) P45/TxD1 P-channel output disable bit (POFF) Parity selection bit (PARS) Functions Name At reset R W 1 0 0 0 2 3 4 5 6 1 7 1 ✕ ✕ ✕ Nothing is arranged for these bits. These are write disabled bits. When these bits are read out, the contents are “1”. 0 1 0: Parity checking disabled 1: Parity checking enabled 0: Even parity 1: Odd parity 0: 1 stop bit 1: 2 stop bits 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) UART3 control register b7 b6 b5 b4 b3 b2 b1 b0 UART3 control register (UART3CON: address 003316) b 0 0 0: 8 bits 1: 7 bits Character length selection bit (CHAS) Parity enable bit (PARE) Stop bit length selection bit (STPS) P35/TxD3 P-channel output disable bit (POFF) Parity selection bit (PARS) Functions Name At reset R W 1 0 0 0 2 3 4 5 6 1 7 1 ✕ ✕ ✕ Nothing is arranged for these bits. These are write disabled bits. When these bits are read out, the contents are “1”. 0 1 0: Parity checking disabled 1: Parity checking enabled 0: Even parity 1: Odd parity 0: 1 stop bit 1: 2 stop bits 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) |
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