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M38048FDHKP Scheda tecnica(PDF) 301 Page - Renesas Technology Corp

Il numero della parte M38048FDHKP
Spiegazioni elettronici  8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  387 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M38048FDHKP Scheda tecnica(HTML) 301 Page - Renesas Technology Corp

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3-11
REJ09B0212-0100Z
Rev.1.00
Jan 14, 2005
3804 Group (Spec.H)
APPENDIX
3.1 Electrical characteristics
Note: When the P45/TxD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
Table 3.1.13 Switching characteristics
(VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Max.
140
200
350
30
35
40
30
35
40
200
250
300
30
35
40
30
35
40
30
35
40
Symbol
Unit
Typ.
0
0
0
10
12
15
10
12
15
Min.
tC(SCLK1)2-30, tC(SCLK3)/2-30
tC(SCLK1)2-35, tC(SCLK3)/2-35
tC(SCLK1)2-40, tC(SCLK3)/2-40
tC(SCLK1)2-30, tC(SCLK3)/2-30
tC(SCLK1)2-35, tC(SCLK3)/2-35
tC(SCLK1)2-40, tC(SCLK3)/2-40
-30
-30
-30
tC(SCLK2)/2-160
tC(SCLK2)/2-200
tC(SCLK2)/2-240
tC(SCLK2)/2-160
tC(SCLK2)/2-200
tC(SCLK2)/2-240
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
Serial I/O1, serial I/O3
clock output “H” pulse width
Serial I/O1, serial I/O3
clock output “L” pulse width
Serial I/O1, serial I/O3
output delay time (Note)
Serial I/O1, serial I/O3
output valid time (Note)
Serial I/O1, serial I/O3
rise time of clock output
Serial I/O1, serial I/O3
fall time of clock output
Serial I/O2
clock output “H” pulse width
Serial I/O2
clock output “L” pulse width
Serial I/O2
output delay time
Serial I/O2
output valid time
Serial I/O2
fall time of clock output
CMOS
rise time of output (Note)
CMOS
fall time of output (Note)
tWH(SCLK1)
tWH(SCLK3)
tWL(SCLK1)
tWL(SCLK3)
td(SCLK1-TxD1)
td(SCLK3-TxD3)
tV(SCLK1-TxD1)
tV(SCLK3-TxD3)
tr(SCLK1)
tr(SCLK3)
tf(SCLK1)
tf(SCLK3)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2-SOUT2)
tV(SCLK2-SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Test
conditions
Fig. 3.1.1



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