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AX2000-1CS896I Scheda tecnica(PDF) 101 Page - Actel Corporation

Il numero della parte AX2000-1CS896I
Spiegazioni elettronici  Axcelerator Family FPGAs
PDF  226 Pages
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Produttore elettronici  ACTEL [Actel Corporation]
Homepage  http://www.actel.com
Logo ACTEL - Actel Corporation

AX2000-1CS896I Scheda tecnica(HTML) 101 Page - Actel Corporation

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Axcelerator Family FPGAs
v2.7
2-87
Table 2-98 • Two FIFO Blocks Cascaded
Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C
'–2' Speed
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
FIFO Module Timing
tWSU
Write Setup
1.39
1.59
1.86
ns
tWHD
Write Hold
0.22
0.25
0.3
ns
tWCKH
WCLK High
0.98
1.11
1.31
ns
tWCKL
WCLK Low
2.29
2.61
3.07
ns
tWCKP
Minimum WCLK Period
4.58
5.22
6.14
ns
tRSU
Read Setup
1.7
1.94
2.28
ns
tRHD
Read Hold
0
0
0
ns
tRCKH
RCLK High
0.95
1.08
1.27
ns
tRCKL
RCLK Low
2.46
2.8
3.29
ns
tRCKP
Minimum RCLK period
4.92
5.6
6.58
ns
tCLRHF
Clear High
1.08
1.23
1.45
ns
tCLR2FF
Clear-to-flag (EMPTY/FULL)
2.02
2.3
2.7
ns
tCLR2AF
Clear-to-flag (AEMPTY/AFULL)
4.62
5.26
6.19
ns
tCK2FF
Clock-to-flag (EMPTY/FULL)
2.24
2.55
3
ns
tCK2AF
Clock-to-flag (AEMPTY/AFULL)
5.31
6.05
7.11
ns
tRCK2RD1
RCLK-To-OUT (Pipelined)
1.51
1.72
2.02
ns
tRCK2RD2
RCLK-To-OUT (Nonpipelined)
2.76
3.14
3.69
ns
Table 2-99 • Four FIFO Blocks Cascaded
Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C
'–2' Speed
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
FIFO Module Timing
tWSU
Write Setup
2.37
2.7
3.17
ns
tWHD
Write Hold
0.22
0.25
0.3
ns
tWCKH
WCLK High
0.98
1.11
1.31
ns
tWCKL
WCLK Low
3.27
3.72
4.37
ns
tWCKP
Minimum WCLK Period
6.54
7.44
8.74
ns
tRSU
Read Setup
3.08
3.51
4.13
ns
tRHD
Read Hold
0
0
0
ns
tRCKH
RCLK High
0.95
1.08
1.27
ns
tRCKL
RCLK Low
3.85
4.39
5.16
ns
tRCKP
Minimum RCLK period
7.7
8.78
10.32
ns
tCLRHF
Clear High
1.08
1.23
1.45
ns
tCLR2FF
Clear-to-flag (EMPTY/FULL)
2.02
2.3
2.7
ns
tCLR2AF
Clear-to-flag (AEMPTY/AFULL)
4.62
5.26
6.19
ns
tCK2FF
Clock-to-flag (EMPTY/FULL)
2.24
2.55
3
ns
tCK2AF
Clock-to-flag (AEMPTY/AFULL)
5.31
6.05
7.11
ns
tRCK2RD1
RCLK-To-OUT (Pipelined)
2.49
2.83
3.33
ns
tRCK2RD2
RCLK-To-OUT (Nonpipelined)
3.36
3.82
4.5
ns



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