ATmega165 datasheet(204/336 Pages) ATMEL

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204

ATmega165/V

2573G–AVR–07/09

•Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input

clock to the ADC.

The ADC Data Register –

ADCL and ADCH

ADLAR = 0

ADLAR = 1

When an ADC conversion is complete, the result is found in these two registers. When

ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently,

if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to

read ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is

read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared

(default), the result is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion

Result” on page 200.

Table 84. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

128

Bit

151413121110

–

ADC9

ADC8

ADCH

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

ADCL

765

43210

Read/Write

RRRRR

RRR

RRRRR

RRR

Initial Value

000

00000

000

00000

Bit

151413121110

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

ADC1

ADC0

–

–––––

ADCL

765

43210

Read/Write

RRRRR

RRR

RRRRR

RRR

Initial Value

000

00000

000

00000

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