ATmega165 datasheet(253/336 Pages) ATMEL

253 / 336 page

253

ATmega165/V

2573G–AVR–07/09

Set XA1, XA0 to “00”. This enables address loading.

Set BS1 to “0”. This selects low address.

Set DATA = Address low byte (0x00 - 0xFF).

Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

Set XA1, XA0 to “01”. This enables data loading.

Set DATA = Data low byte (0x00 - 0xFF).

Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

Set BS1 to “1”. This selects high data byte.

Set XA1, XA0 to “01”. This enables data loading.

Set DATA = Data high byte (0x00 - 0xFF).

Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

Set BS1 to “1”. This selects high data byte.

Give PAGEL a positive pulse. This latches the data bytes. (See Figure 113 for

signal waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page is

loaded.

While the lower bits in the address are mapped to words within the page, the higher bits

address the pages within the FLASH. This is illustrated in Figure 112 on page 254. Note

that if less than eight bits are required to address words in the page (pagesize < 256),

the most significant bit(s) in the address low byte are used to address the page when

performing a Page Write.

G. Load Address High byte

Set XA1, XA0 to “00”. This enables address loading.

Set BS1 to “1”. This selects high address.

Set DATA = Address high byte (0x00 - 0xFF).

Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

Give WR a negative pulse. This starts programming of the entire page of data.

RDY/BSY goes low.

Wait until RDY/BSY goes high (See Figure 113 for signal waveforms).

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

1. Set XA1, XA0 to “10”. This enables command loading.

Set DATA to “0000 0000”. This is the command for No Operation.

Give XTAL1 a positive pulse. This loads the command, and the internal write sig-

nals are reset.

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