ATmega32U2 datasheet(214/314 Pages) ATMEL

214 / 314 page

214

7799B–AVR–07/09

ATmega8U2/16U2/32U2

21.18.8

UENUM – USB Endpoint Number Register

• Bits 7:3 – Res: Reserved

These bits are reserved and will always read as zero.

• Bits 2:0 – EPNUM[2:0] Endpoint Number Bits

Writing these bits allows to select the hardware endpoint number that can be accessed by the

CPU interface. This register select the target endpoint number for UECONEX, UECFG0X,

UECFG1X, UESTA0X, UESTA1X, UEINTX, UEIENX, UEDATX, UEBCLX registers. See “End-

point selection” on page 198 for more details.

21.18.9

UERST – USB Endpoint Reset Register

• Bits 7:5 – Res: Reserved

These bits are reserved and will always read as zero.

• Bits 4:0 – EPRST[4:0]: Endpoint FIFO Reset Bits

Writing this bit to one keeps the selected endpoint (UENUM register value) under reset state.

selected. Writing this bit to zero completes the endpoint reset operation and makes the endpoint

usable. See “Endpoint reset” on page 197 for more information.

21.18.10 UECONX – USB Endpoint Control Register

• Bits 7:6 – Res: Reserved

These bits are reserved and will always read as zero.

• Bit 5 – STALLRQ: STALL Request Handshake Bit

Writing this bit to one allows the USB controller to generate a STALL answer for the next SETUP

transaction received. This bit is cleared by hardware when the STALL handshake is sent or

when a new SETUP token is received. Writing this bit to zero has no effect. The STALL hand-

shake can be abort using STALLRQC bit.

See “STALL request” on page 201 for more details.

Bit

210

(0xE9)

EPNUM[2:0]

UENUM

Read/Write

RRR

R/W

Initial Value

Bit

321

(0xEA)

EPRST D4

EPRST D3

EPRST D2

EPRST D1

EPRST D0

UERST

Read/Write

R/W

Initial Value

Bit

(0xEB)

STALLRQ

STALLRQC

RSTDT

EPEN

UECONX

Read/Write

R/W

Initial Value

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