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68HC705SP7 Scheda tecnica(PDF) 129 Page - Freescale Semiconductor, Inc

Il numero della parte 68HC705SP7
Spiegazioni elettronici  General Release Specification
PDF  230 Pages
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Produttore elettronici  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

68HC705SP7 Scheda tecnica(HTML) 129 Page - Freescale Semiconductor, Inc

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Analog Subsystem
Voltage Measurement Methods
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Analog Subsystem
voltage on the negative input (–). All A/D conversion methods should
have a maximum time check to determine if this case is occurring.
Once the maximum timeout detection has been made, the state of the
comparator outputs can be tested in order to determine the situation.
However, such tests should be carefully designed when using modes 1,
2, or 3 as these modes cause the immediate automatic discharge of the
external ramping capacitor before any software check can be made of
the output state of comparator 2.
NOTE:
All A/D conversion methods should include a test for a maximum
elapsed time in order to detect error cases where the inputs may be
outside of the design specification.
8.7.1 Absolute Voltage Readings
The absolute value of a voltage measurement can be calculated in
software by first taking a reference reading from a fixed source and then
comparing subsequent unknown voltages to that reading as a
percentage of the reference voltage multiplied times the known
reference value.
The accuracy of absolute readings will depend on the error sources
taken into account using the features of the analog subsystem and
appropriate software as described in Table 8-6. As can be seen from this
table, most of the errors can be reduced by frequent comparisons to a
known voltage, use of the inverted comparator inputs, and averaging of
multiple samples.
8.7.1.1 Internal Absolute Reference
If a stable source of VDD is provided, the reference measurement point
can be internally selected. In this case the reference reading can be
taken by setting the VREF bit and clearing the MUX1:4 bits in the AMUX
register. This connects the channel selection bus to the VDD pin. In order
to stay within the VMAX range the DHOLD bit should be used to select
the 1/2 divided input.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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