68HC705SP7 datasheet(164/230 Pages) FREESCALE

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Programmable Timer

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Programmable Timer

11.6 Output Compare Registers (OCRH and OCRL)

The output compare function is a means of generating an output signal

when the 16-bit timer counter reaches a selected value as shown in

Figure 11-8. Software writes the selected value into the output compare

registers. On every fourth internal clock cycle (every eight oscillator

clock cycles) the output compare circuitry compares the value of the

free-running timer counter to the value written in the output compare

registers. When a match occurs, the timer transfers the output level

(OLVL) from the timer control register (TCR) to the PB4/AN4/TCMP pin.

Software can use the output compare register to measure time periods,

to generate timing delays, or to generate a pulse of specific duration or

a pulse train of specific frequency and duty cycle on the PB4/AN4/TCMP

pin.

Figure 11-8. Timer Output Compare Block Diagram

OCRH ($0016)

16-BIT COUNTER

÷ 4

INTERNAL

(OSC

÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

OUTPUT COMPARE

RESET

CLOCK

INTERRUPT

OCRL ($0017)

TIMER STATUS REG.

$0012

$0013

INTERNAL

($FFFC)

DATA

R/W

OCRH

R/W

OCRL

BUS

PB4

AN4

TCMP

EDGE

SELECT

DETECT

LOGIC

16-BIT COMPARATOR

(OCF)

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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