MAC7200 datasheet(279/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

201

Figure 12-1. DMA Block Diagram

12.2.1

Overview

The DMA is a highly-programmable data transfer engine, which has been optimized to minimize the

required intervention from the host processor. It is intended for use in applications where the data size to

be transferred is statically known, and is not defined within the data packet itself. The DMA hardware

supports:

•

Single design supporting 16-, 32- and 64-channel implementations, dependent on size of the TCD

memory and design parameters (the MAC72xx family of devices has 16 channels)

•

Connections to the AMBA-AHB crossbar switch for bus mastering the data movement, IPS slave

bus for programming the module

— Parameterized support for 32- and 64-bit AMBA-AHB data path widths

•

32-byte transfer control descriptor per channel stored in local memory

j+1

n-1

SRAM

Transfer

Control

Descriptor (TCD)

dma_engine

addr_path

data_path

DMA

IPS

Bus

AMBA

AHB

ipd_req[n-1:0]

dma_ipi_int[n-1:0]

pmodel_charb

addr

wdata[31:0]

rdata[31:0]

hrdata[{63,31}:0]

hwdata[{63,31}:0]

haddr[31:0]

Bus

dma_ipd_done[n-1:0]

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