SPMCK16Z4MPV16 datasheet(245/500 Pages) FREESCALE

245 / 500 page

M68HC16 Z SERIES

MULTICHANNEL COMMUNICATION INTERFACE

USER’S MANUAL

10-5

Figure 10-2 SPI Block Diagram

Clock control logic allows a selection of clock polarity and a choice of two clocking pro-

tocols to accommodate most available synchronous serial peripheral devices. When

the SPI is configured as a master, software selects one of 254 different bit rates for the

serial clock.

During an SPI transfer, data is simultaneously transmitted (shifted out serially) and re-

ceived (shifted in serially). A serial clock line synchronizes shifting and sampling of the

information on the two serial data lines. A slave-select line allows individual selection

of a slave SPI device. Slave devices which are not selected do not interfere with SPI

bus activities. On a master SPI device the slave-select line can optionally be used to

indicate a multiple-master bus contention.

MCCI SPI BLOCK

MISO

PMC0

MOSI

PMC1

SCK

PMC2

PMC3

SPI CONTROL

SHIFT

CONTROL

LOGIC

CLOCK

SPI CONTROL REGISTER

SELECT

SPI CLOCK (MASTER)

CLOCK

SPI STATUS REGISTER

MSTR

SPE

SPI INTERRUPT

INTERNAL

DATA BUS

REQUEST

LOGIC

8/16-BIT SHIFT REGISTER

READ DATA BUFFER

MSB

LSB

MODULUS

COUNTER

INTERNAL

MCU CLOCK

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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