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SPMCK16Z4MPV16 Scheda tecnica(PDF) 322 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV16 Scheda tecnica(HTML) 322 Page - Freescale Semiconductor, Inc |
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322 / 500 page  ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A-38 USER’S MANUAL Table A-21 20.97-MHz Background Debug Mode Timing (V DD and V DDSYN = 5.0 Vdc ± 5%, V SS = 0 Vdc, T A = T L to T H) 1 NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. Num Characteristic Symbol Min Max Unit B0 DSI Input Setup Time tDSISU 15 — ns B1 DSI Input Hold Time tDSIH 10 — ns B2 DSCLK Setup Time tDSCSU 15 — ns B3 DSCLK Hold Time tDSCH 10 — ns B4 DSO Delay Time tDSOD —25 ns B5 DSCLK Cycle Time tDSCCYC 2— tcyc B6 CLKOUT High to FREEZE Asserted/Negated tFRZAN —50 ns B7 CLKOUT High to IPIPE1 High Impedance tIFZ —50 ns B8 CLKOUT High to IPIPE1 Valid tIF —50 ns B9 DSCLK Low Time tDSCLO 1— tcyc B10 IPIPE1 High Impedance to FREEZE Asserted tIPFA TBD — tcyc B11 FREEZE Negated to IPIPE[0:1] Active tFRIP TBD — tcyc Table A-22 25.17-MHz Background Debug Mode Timing (V DD and V DDSYN = 5.0 Vdc ± 5%, V SS = 0 Vdc, T A = T L to T H) 1 NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. Num Characteristic Symbol Min Max Unit B0 DSI Input Setup Time tDSISU 10 — ns B1 DSI Input Hold Time tDSIH 5— ns B2 DSCLK Setup Time tDSCSU 10 — ns B3 DSCLK Hold Time tDSCH 5— ns B4 DSO Delay Time tDSOD —20 ns B5 DSCLK Cycle Time tDSCCYC 2— tcyc B6 CLKOUT High to FREEZE Asserted/Negated tFRZAN —20 ns B7 CLKOUT High to IPIPE1 High Impedance tIFZ —20 ns B8 CLKOUT High to IPIPE1 Valid tIF —20 ns B9 DSCLK Low Time tDSCLO 1— tcyc B10 IPIPE1 High Impedance to FREEZE Asserted tIPFA TBD — tcyc B11 FREEZE Negated to IPIPE[0:1] Active tFRIP TBD — tcyc Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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