SPMCK16Z4MPV16 datasheet(184/500 Pages) FREESCALE

184 / 500 page

MASKED ROM MODULE

M68HC16 Z SERIES

7-2

USER’S MANUAL

The MRM array can be mapped to any 8-Kbyte boundary in the memory map, but must

not overlap other module control registers (overlap makes the registers inaccessible).

If the array overlaps the MRM register block, addresses in the register block are ac-

cessed instead of the corresponding ROM array addresses.

ROMBAH and ROMBAL can only be written while the ROM is in low-power stop mode

(MRMCR STOP = 1) and the base address lock (MRMCR LOCK = 0) is disabled.

LOCK can be written once only to a value of one; subsequent writes are ignored. This

prevents accidental remapping of the array.

7.3 MRM Array Address Space Type

ASPC[1:0] in MRMCR determines ROM array address space type. The module can

respond to both program and data space accesses or to program space accesses

only. The default value of ASPC[1:0] is established during mask programming, but the

value can be changed after reset if the LOCK bit in the MRMCR has not been masked

to a value of one. Because the CPU16 operates in supervisor mode only, ASPC1 has

no effect.

Table 7-1 shows ASPC[1:0] field encodings.

Refer to 5.5.1.7 Function Codes for more information concerning address space

types and program/data space access. Refer to 4.6 Addressing Modes for more in-

formation on addressing modes.

7.4 Normal Access

The array can be accessed by byte, word, or long word. A byte or aligned word access

takes a minimum of one bus cycle (two system clocks). A long word or misaligned

word access requires a minimum of two bus cycles.

Access time can be optimized for a particular application by inserting wait states into

each access. The number of wait states inserted is determined by the value of

WAIT[1:0] in the MRMCR. Two, three, four, or five clock accesses can be specified.

The default value WAIT[1:0] is established during mask programming, but field value

can be changed after reset if the LOCK bit in the MRMCR has not been masked to a

value of one.

Table 7-2 shows WAIT[1:0] field encodings.

Table 7-1 ROM Array Space Field

ASPC[1:0]

State Specified

Program and data accesses

Program access only

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

SPMCK16Z4MPV16 Scheda tecnica(PDF) 184 Page - Freescale Semiconductor, Inc

SPMCK16Z4MPV16 Scheda tecnica(HTML) 184 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL