SPMCK16Z4MPV20 datasheet(273/500 Pages) FREESCALE

273 / 500 page

M68HC16 Z SERIES

GENERAL-PURPOSE TIMER

USER’S MANUAL

11-9

Figure 11-2 Prescaler Block Diagram

In the prescaler, the system clock is divided by a nine-stage divider chain. Prescaler

outputs equal to system clock divided by 2, 4, 8, 16, 32, 64, 128, 256 and 512 are pro-

vided. Connected to these outputs are two multiplexers, one for the capture/compare

unit, the other for the PWM unit.

Multiplexers can each select one of seven prescaler taps or an external input from the

PCLK pin. Multiplexer output for the timer counter (TCNT) is selected by bits CPR[2:0]

in timer interrupt mask register 2 (TMSK2). Multiplexer output for the PWM counter

(PWMCNT) is selected by bits PPR[2:0] in PWM control register C (PWMC). After re-

set, the GPT is configured to use system clock divided by four for TCNT and system

clock divided by two for PWMCNT. Initialization software can change the division fac-

tor. The PPR bits can be written at any time, but the CPR bits can only be written once

after reset, unless the GPT is in test or freeze mode.

GPT PRE BLOCK

CPR2 CPR1 CPR0

TO PULSE ACCUMULATOR

TO CAPTURE/

COMPARE

TIMER

SELECT

DIVIDER

256

128

SYSTEM CLOCK

512

PPR2 PPR1 PPR0

PWM UNIT

SELECT

128

TO PULSE ACCUMULATOR

EXT.

SYNCHRONIZER AND

DIGITAL FILTER

EXT.

PCLK

Freescale Semiconductor, Inc.

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