SPMCK16Z4MPV20 datasheet(130/500 Pages) FREESCALE

130 / 500 page

SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-24

USER’S MANUAL

5.4 System Protection

The system protection block preserves reset status, monitors internal activity, and pro-

vides periodic interrupt generation. Figure 5-8 is a block diagram of the submodule.

Figure 5-8 System Protection

5.4.1 Reset Status

The reset status register (RSR) latches internal MCU status during reset. Refer to

5.7.10 Reset Status Register for more information.

5.4.2 Bus Monitor

The internal bus monitor checks data size acknowledge (DSACK) or autovector

(AVEC) signal response times during normal bus cycles. The monitor asserts the in-

ternal bus error (BERR) signal when the response time is excessively long.

DSACK and AVEC response times are measured in clock cycles. Maximum allowable

response time can be selected by setting the bus monitor timing (BMT[1:0]) field in the

system protection control register (SYPCR). Table 5-8 shows the periods allowed.

SYS PROTECT BLOCK

MODULE CONFIGURATION

AND TEST

RESET STATUS

HALT MONITOR

BUS MONITOR

SPURIOUS INTERRUPT MONITOR

SOFTWARE WATCHDOG TIMER

PERIODIC INTERRUPT TIMER

29 PRESCALER

CLOCK

IRQ[7:1]

BERR

RESET REQUEST

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SPMCK16Z4MPV20 Scheda tecnica(PDF) 130 Page - Freescale Semiconductor, Inc