SPMCK16Z4MPV20 datasheet(149/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-43

Figure 5-16 LPSTOP Interrupt Mask Level

5.6.5 Bus Exception Control Cycles

An external device or a chip-select circuit must assert at least one of the DSACK[1:0]

signals or the AVEC signal to terminate a bus cycle normally. Bus exception control

cycles are used when bus cycles are not terminated in the expected manner. There

are two sources of bus exception control cycles.

• Bus error signal (BERR)

— When neither DSACK nor AVEC is asserted within a specified period after as-

sertion of AS, the internal bus monitor asserts internal BERR.

— The spurious interrupt monitor asserts internal BERR when an interrupt re-

quest is acknowledged and no IARB contention occurs. BERR assertion termi-

nates a cycle and causes the MCU to process a bus error exception.

— External devices can assert BERR to indicate an external bus error.

• Halt signal (HALT)

— HALT can be asserted by an external device to cause single bus cycle opera-

tion. HALT is typically used for debugging purposes.

To control termination of a bus cycle for a bus error condition properly, DSACK, BERR,

and HALT must be asserted and negated synchronously with the rising edge of

CLKOUT. This ensures that setup time and hold time requirements are met for the

same falling edge of the MCU clock when two signals are asserted simultaneously.

Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information. Ex-

ternal circuitry that provides these signals must be designed with these constraints in

mind, or the internal bus monitor must be used.

Table 5-17 is a summary of the acceptable bus cycle terminations for asynchronous

cycles in relation to DSACK assertion.

LPSTOP MASK LEVEL

IP MASK

000

0000000000

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