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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

116

Document Number: 306261-004US

5.6.1.4

UTOPIA Level 2 Clock Timings

5.6.1.5

Expansion Bus Clock Timings

5.6.2

Bus Signal Timings

The AC timing waveforms are shown in the following sections.

5.6.2.1

PCI

Table 51.

UTOPIA Level 2 Clock Timings

Symbol

Parameter

Min.

Nom.

Max.

Units

Notes

Tperiod

Clock period for Tx and Rx UTOPIA Level 2

clocks

30.303

Tduty

Duty cycle for Tx and Rx UTOPIA Level 2

clocks

Trise/fall

Rise and fall time requirements for Tx and

Rx UTOPIA Level 2 clocks

2ns

Table 52.

Expansion Bus Clock Timings

Symbol

Parameter

Min.

Nom.

Max.

Units

Notes

Tperiod

Clock period for expansion bus clock

12.5

Tduty

Duty cycle for expansion bus clock

Trise/fall

Rise and fall time requirements for

expansion bus clock

2ns

Figure 17.

PCI Output Timing

Note:

VHI = 0.6 VCC and VLOW = 0.2 VCC.

A9572-01

CLK

Output

Delay

Tclk2out(b)

Vlow

Vhi

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