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ST10F272Z2 Scheda tecnica(PDF) 106 Page - STMicroelectronics |
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ST10F272Z2 Scheda tecnica(HTML) 106 Page - STMicroelectronics |
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106 / 189 page ![]() System reset ST10F272Z2 106/189 Figure 35. PORT0 bits latched into the different registers after reset L.5 L.4 L.3 L.2 L.1 L.0 H.3 H.2 H.1 H.0 L.7 L.6 H.7 H.6 H.5 H.4 EMU ADP WRC CSSEL SALSEL BUSTYP RP0H Clock Port 4 Logic Port 6 Logic SYSCON BUSCON0 Internal Control Logic CLKCFG 76 2 P0L.7 P0L.7 9 BYTDIS WRCFG PORT0 Bootstrap Loader Generator CLKCFG SALSEL CSSEL WRC BTYP BSL Res. 10 9 ALE CTL0 BUS ACT0 EA / VSTBY ROMEN 10 8 7 |
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