PIC16F1946 datasheet(216/448 Pages) MICROCHIP

216 / 448 page

PIC16(L)F1946/1947

DS41414C-page 216

Preliminary

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23.2

Compare Mode

The Compare mode function described in this section

is available and identical for CCP modules ECCP1,

ECCP2, ECCP3, CCP4 and CCP5.

Compare mode makes use of the 16-bit Timer1

resource. The 16-bit value of the CCPRxH:CCPRxL

value of the TMR1H:TMR1L register pair. When a

match occurs, one of the following events can occur:

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPxCON register. At

the same time, the interrupt flag CCPxIF bit is set.

All Compare modes can generate an interrupt.

Figure 23-2 shows a simplified diagram of the

Compare operation.

FIGURE 23-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

23.2.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

Also, the CCPx pin function can be moved to

alternative pins using the APFCON register. Refer to

Section 12.1 “Alternate Pin Function”

for more

details.

23.2.2

TIMER1 MODE RESOURCE

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

See Section 21.0 “Timer1 Module with Gate Control”

for more information on configuring Timer1.

23.2.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPx module does not

assert control of the CCPx pin (see the CCPxCON

23.2.4

SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen

(CCPxM<3:0> = 1011), the CCPx module does the

following:

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

The CCPx module does not assert control of the CCPx

pin in this mode.

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPRxH, CCPRxL regis-

ter pair. The TMR1H, TMR1L register pair is not reset

until the next rising edge of the Timer1 clock. The Spe-

cial Event Trigger output starts an A/D conversion (if

the A/D module is enabled). This allows the CCPRxH,

CCPRxL register pair to effectively provide a 16-bit pro-

grammable period register for Timer1.

Refer to Section 16.0 “Analog-to-Digital Converter

(ADC) Module”

for more information.

Note:

Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the PORT I/O

data latch.

CCPRxH CCPRxL

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCPxIF Interrupt Flag

(PIRx)

Match

TRIS

CCPxM<3:0>

Mode Select

Output Enable

CCPx

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

mode. In order for Capture mode to

recognize the trigger event on the CCPx

pin, TImer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

TABLE 23-3:

SPECIAL EVENT TRIGGER

Device

CCPx/ECCPx

PIC16F/LF1946/47

CCP5

Note 1:

The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 register.

Removing the match condition by

changing the contents of the CCPRxH

and CCPRxL register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates

the

Timer1

Reset,

will

preclude the Reset from occurring.

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