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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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PIC16F1946 Scheda tecnica(PDF) 310 Page - Microchip Technology |
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PIC16F1946 Scheda tecnica(HTML) 310 Page - Microchip Technology |
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310 / 448 page  PIC16(L)F1946/1947 DS41414C-page 310 Preliminary 2010-2011 Microchip Technology Inc. 25.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. The SPxBRGH:SPxBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored. Example 25-1 provides a sample calculation for deter- mining the desired baud rate, actual baud rate, and baud rate% error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 25-5. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. EXAMPLE 25-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Solving for SPxBRGH:SPxBRGL: SPxBRGH: SPxBRGL FOSC Desired Baud Rate --------------------------------------------- 64 --------------------------------------------- 1 – = Desired Baud Rate FOSC 64 [SPxBRGH:SPxBRG] 1 + -------------------------------------------------------------------------- = 16000000 9600 ------------------------ 64 ------------------------1 – = 25.042 25 == ActualBaudRate 16000000 64 25 1 + --------------------------- = 9615 = Calc. Baud Rate Desired Baud Rate – Desired Baud Rate -------------------------------------------------------------------------------------------- 9615 9600 – 9600 ---------------------------------- 0.16% == Baud Rate % Error = TABLE 25-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 00 0 8-bit/Asynchronous FOSC/[64 (n+1)] 00 1 8-bit/Asynchronous FOSC/[16 (n+1)] 01 0 16-bit/Asynchronous 01 1 16-bit/Asynchronous FOSC/[4 (n+1)] 10 x 8-bit/Synchronous 11 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPxBRGH, SPxBRGL register pair |
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