PIC16F1946 datasheet(124/448 Pages) MICROCHIP

124 / 448 page

PIC16(L)F1946/1947

DS41414C-page 124

Preliminary

 2010-2011 Microchip Technology Inc.

TABLE 11-3:

SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

bit 3

WRERR:

EEPROM Error Flag bit

= Condition indicates an improper program or erase sequence attempt or termination (bit is set

automatically on any set attempt (write ‘1’) of the WR bit).

= The program or erase operation completed normally.

bit 2

WREN:

Program/Erase Enable bit

= Allows program/erase cycles

= Inhibits programming/erasing of program Flash and data EEPROM

bit 1

WR:

Write Control bit

= Initiates a program Flash or data EEPROM program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete.

The WR bit can only be set (not cleared) in software.

= Program/erase operation to the Flash or data EEPROM is complete and inactive.

bit 0

RD:

Read Control bit

= Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in

hardware. The RD bit can only be set (not cleared) in software.

= Does not initiate a program Flash or data EEPROM data read.

EECON2: EEPROM CONTROL 2 REGISTER

W-0/0

EEPROM Control Register 2

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

S = Bit can only be set

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

Data EEPROM Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

EECON1 register. The value written to this register is used to unlock the writes. There are specific

timing requirements on these writes. Refer to Section 11.2.2 “Writing to the Data EEPROM

Memory”

for more information.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

EECON1

EEPGD

CFGS

LWLO

FREE

WRERR

WREN

123

EECON2

EEPROM Control Register 2 (not a physical register)

111*

EEADRL

EEADRL<7:0>

122

EEADRH

—

EEADRH<6:0>

123

EEDATL

EEDATL<7:0>

122

EEDATH

—

EEDATH<5:0>

122

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

PIE2

OSFIE

C2IE

C1IE

EEIE

BCLIE

LCDIE

C3IE

CCP2IE

PIR2

OSFIF

C2IF

C1IF

EEIF

BCLIF

LCDIF

C3IF

CCP2IF

Legend:

—

= unimplemented location, read as ‘0’. Shaded cells are not used by Data EEPROM module.

Page provides register information.

EECON1: EEPROM CONTROL 1 REGISTER (CONTINUED)

PIC16F1946 Scheda tecnica(PDF) 124 Page - Microchip Technology

PIC16F1946 Scheda tecnica(HTML) 124 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL